1. Field of the Invention
This invention relates to a semiconductor memory device, for example, a memory cell of a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
FIG. 10 shows an equivalent circuit of a memory cell of a DRAM having a conventional stacked capacitor structure. The memory cell includes a selection transistor Q1 and a data storing capacitor C.sub.S. The gate of the selection transistor Q1 is connected to a word line WL, and one end of the current path of the selection transistor Q1 is connected to a bit line BL and the other end of the current path thereof is connected to the capacitor C.sub.S.
FIGS. 11 and 12 show the structure of the above memory cell and portions which are the same as those of FIG. 10 are denoted by the same reference numerals.
In FIGS. 11 and 12, a pair of polysilicon layers 31 and 32 constituting the capacitor C.sub.S are formed above a diffusion layer n.sup.+ of the selection transistor Q1. That is, the polysilicon layer 31 is formed in valid contact with the diffusion layer n.sup.+ of the selection transistor Q1 and the polysilicon layer 32 serving as a plate electrode which is formed above the polysilicon layer 31 with an insulation film disposed therebetween is biased to a preset potential. The pair of polysilicon layers 31 and 32 are formed to extend over the word line WL partly acting as the gate electrode of the selection transistor Q1 to increase the storage capacity.
In the DRAM, the number of memory cells connected to the bit line increases and the capacitance associated with the bit line tends to increase with formation of the memory cell of even greater miniaturization. Further, as the miniaturization processing technique has been developed, the occupied area of each cell is reduced. Therefore, the technique for making the insulation film of the capacitor thinner is required to obtain the memory capacitance C.sub.S of a desired value. However, there is a limitation on the technique of reducing the film thickness of the insulation film since it is necessary to maintain the reliability of the capacitor, for example. Therefore, it becomes difficult to attain a desired value of a so-called C.sub.B /C.sub.S ratio which is the ratio of the capacitance C.sub.B of the bit line to the memory capacitance C.sub.S of the cell.
Further, in the LSI of the extremely fine pattern processing generation in the future, it is considered that the power source voltage will be made lower than 5 V. When the power source voltage of the DRAM is lowered, the amount of charges stored in the capacitor is reduced so that the amount of charges transferred to the bit line in the data readout operation will become small. Therefore, it is considered difficult to correctly amplify data by use of a sense amplifier. Now, the relation between the capacitance C.sub.B of the bit line and the memory capacitance C.sub.S of the cell is explained. FIG. 13 shows a conventional DRAM including a peripheral circuit and FIG. 14 illustrates the operation of the circuit shown in FIG. 13. The bit line potential V.sub.BL is an initial preset potential of the bit line before the readout operation.
First, the readout operation is explained.
(1) Since the equalizing signal EQL is set at a high level before the active cycle is started, the bit lines BL0 to BL3 are precharged to a potential of V.sub.BL level. PA1 (2) A word line WL0 is selected by a row decoder (not shown) and the potential of the word line WL0 is raised to 7.5 V which is higher than Vcc (=5 v) by means of a bootstrap circuit (not shown). PA1 (3) A dummy word line DWL0 and /DWL0 (/indicates an inverted form) corresponding to the selected word line are selected, and the potential of the dummy word line DWL0 is set from the V.sub.BL level to the Vcc level and the potential of the dummy word line /DWL0 is set from the V.sub.BL to the Vss level. PA1 (4) Data "1" stored in the selected cell connected to the bit line BL0 and data "0" stored in the selected cell connected to the bit line BL2 are respectively transferred to the bit lines BL0 and BL2. Assuming that the storage level of data "1" in the memory cell is V.sub.1 and the storage level of data "0" is V.sub.0, then the potential level v.sub.1 of the bit line after the readout of data "1" can be expressed by the following equation (1): EQU v.sub.1 =(V.sub.1 +C.sub.B /C.sub.S .multidot.V.sub.BL) / (1+C.sub.B /C.sub.S) (1) PA1 (5) The sense amplifier is activated, the potentials of the bit lines BL0 and BL3 are amplified to the vcc level, and the potentials of the bit lines BL1 and BL2 are amplified to the Vss level. PA1 (6) The potentials of a pair of bit lines BL0 and BL1 or bit lines BL2 and BL3 selected by a selection signal supplied from a column decoder (not shown) to a column selection line CSL are respectively supplied to output lines DQ and/DQ. PA1 a selection transistor having a gate connected to a word line and a current path connected at one end to a bit line; PA1 a capacitor having a storage node connected to the other end of the current path of the selection transistor and a plate electrode insulated from the storage node, an inverted layer being formed in that portion of the plate electrode which is disposed in opposition to the storage node according to data stored in the storage node; and PA1 pulse generation means connected to the plate electrode, for supplying a pulse signal to the plate electrode.
Also, the potential level v.sub.0 of the bit line 10 after the readout of data "0" can be expressed by the following equation (2): EQU v.sub.0 =(V.sub.0 +C.sub.B /C.sub.S .multidot.V.sub.BL) / (1+C.sub.B /C.sub.S) (2)
If V.sub.1 =5 V, V.sub.0 =0 V, V.sub.BL =2.5 V, and C.sub.B /C.sub.S =15, then v.sub.1 =2.656 V and v.sub.0 =2.344 V. Since the reference level of the bit lines BL1 and BL3 is V.sub.BL =2.5 V, the potential difference .increment.v amplified by the sense amplifier becomes equal to .increment.v.sub.1 =0.156 V at the readout time of data "1" and becomes equal to .increment.v.sub.0 =0.156 V at the readout time of data "0", and thus the potential difference is set to the same value at the readout time of data "1" and "0".
Next, the write-in operation is explained. In the write-in operation, the same steps (1) to (3) as described in the readout operation are effected. After this, in the step (4), write-in potentials supplied to the output lines DQ and/DQ are transferred to the sense 10 amplifier via a column switching transistor selected by means of the column selection line CSL. The potentials of the pair of bit lines are set to the Vcc and Vss levels by means of the sense amplifier and data corresponding to the thus set levels is written into a selected memory cell.
In this case, the equations (1) and (2) can be rewritten as follows. EQU v.sub.1 =V.sub.BL +(V.sub.1 -V.sub.BL) / (1+C.sub.B /C.sub.S)(3) EQU v.sub.0 =V.sub.BL +(V.sub.0 -V.sub.BL) / (1+C.sub.B /C.sub.S)(4)
As is clearly seen from the equations (3) and (4), v.sub.1 and v.sub.0 become nearer to V.sub.BL when the capacitance C.sub.B of the bit line increases and the capacitance C.sub.S of the capacitor decreases with an increase in the memory capacitance and with formation of the memory cell of even greater miniaturization.
Since an amplification reference voltage of the sense amplifier is V.sub.BL, the potential differences .increment.v.sub.1 and .increment.v.sub.0 amplified by the sense amplifier are both lowered. Therefore, it becomes difficult to correctly amplify data by use of the sense amplifier.